Solid-state imaging devices enjoy widespread use in contemporary imaging systems. Popular solid-state imaging devices include charge-coupled devices (CCD) and CMOS image sensors (CIS). Such devices are commonly employed in digital still cameras, digital video cameras, cellular telephones, and security systems.
The solid state imaging device converts transmitted light in the form of photon energy to electrical signals, and the electrical signals are converted to information that can be presented on display devices or otherwise processed by a computer system. CCD and CIS imaging devices include photo-reception elements such as photodiodes. Therefore, a significant factor in the efficiency and efficacy of such devices is the ability of the photo-reception elements to convert available photons to electrons. If the photon count being transmitted to the photo-reception elements is less than a threshold amount, the information presented on the display is adversely affected.
FIG. 1 is a sectional view of a conventional solid state imaging device. An n type photodiode device region 12 is formed in a substrate 10. A p+ doped region 14 is formed in the substrate 10 adjacent the photodiode device region 12. The p+ doped region 14 operates as a channel stop region, or insulative region, to prevent the flow of electrons between adjacent imaging devices on the substrate. A gate dielectric layer 16 comprising SiO2 or oxide-nitride-oxide (ONO) and a polysilicon transfer gate layer 18 are then formed on the substrate 10 and patterned to expose the photodiode device region 12 and to thereby form a transfer gate structure at side regions of the photodiode device region 12.
An anti-reflection layer 30 is formed on the resulting structure. A cross-sectional close-up view of an anti-reflection layer is shown in FIG. 2. The anti-reflection layer 30 includes a first dielectric layer 31 comprising silicon dioxide and a second dielectric layer 33 comprising silicon nitride. The anti-reflection layer 30 reduces the number of reflected photons that are incident on the photodiode device 12, and therefore leads to improved efficiency in the photon-to-electrical energy transfer. Absent an anti-reflection layer 30, the reflectivity of photon energy at the surface of the photodiode device region 12 is on the order of 20%-30%. The presence of the conventional anti-reflection layer 30 shown in FIGS. 1 and 2 improves the reflectance level to a reduced amount on the order of 10%-20%. Returning to FIG. 1, a buffer layer 36 comprising silicon dioxide is formed over the top of the second dielectric layer 33 of the anti-reflection layer.
A protective shield layer 60 comprising tungsten is layered over the resulting structure, and is patterned to expose the anti-reflection layer 30 and buffer layer 36 in the photodiode device region 12. The protective shield layer 60 prevents photon energy from directly entering the transfer gate 18. A planarization layer 62 comprising silicon dioxide is then provided on the resulting structure and planarized, for example using chemical-mechanical polishing (CMP). A microlens 64 formed of resin is formed on the top of the planarization layer 62.
With the trend toward ever-increasing integration of solid state imaging devices, compact design and increased pixel density are of primary concern. With these goals in mind, the amount of light available at the light-receiving region of the device has been reduced, due to the reduced device size, thereby limiting device sensitivity. To improve sensitivity, the microlens 64 is provided to focus the incident light into the photodiode device region 12. At the same time, the anti-reflection layer 30 reduces the amount of reflected light and therefore enhances the capture of light energy at the photodiode device region 12.
Japanese patent publication JP 2003-224250 provides an example of a double-layered anti-reflection layer comprising a sequentially formed structure as follows: first silicon dioxide layer/first silicon nitride layer/second silicon dioxide layer/second silicon nitride layer. Each combined silicon dioxide/silicon nitride layer pair forms one anti-reflection layer. This configuration provides for further reduced reflectivity as compared to the single anti-reflection layer configuration of FIG. 2
FIG. 3 is an experimental graph illustrating reflectance as a function of the wavelength of light as a result of the application of first and second anti-reflection layers of the double-layered embodiment of JP 2003-224250. It can be seen in this graph that the application of the second anti-reflection layer operates to reduce reflectance in the visible light wavelength region of about 500-700 nm, as compared to the single reflection layer. However, the reflectance level of the double-layered configuration is actually higher than the single-layered configuration in approximately the 400-500 nm wavelength region, and the double-layered configuration still demonstrates at least 4% reflectance in the visible wavelengths, an amount that can be limiting to device effectiveness as device integration continues.